Exploiting subarrays inside a bank to improve phase change memory performance

  title={Exploiting subarrays inside a bank to improve phase change memory performance},
  author={Jianhui Yue and Yifeng Zhu},
  journal={2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)},
Enabling subarrays reduces memory latency by allowing concurrent accesses to different subarrays within the same bank in the DRAM system. However, this technology has great challenges in the PCM system since an on-going write cannot overlap with other accesses due to large electric current draw for writes. This paper proposes two new mechanisms (PASAK and WAVAK) that leverage subarray-level parallelism to enable a bank to serve a write and multiple reads in parallel without violating power… CONTINUE READING
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A 0.1-um 1.8-v 256-mb phasechange random access memory (pram) with 66-mhz synchronous burstread operation

  • S. Kang, W. Y. Cho, B.-H. Cho
  • Solid-State Circuits, IEEE Journal of, vol. 42…
  • 2007
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