Exploiting regularity for low-power design

  title={Exploiting regularity for low-power design},
  author={Renu Mehra and Jan M. Rabaey},
  journal={Proceedings of International Conference on Computer Aided Design},
Current day behavioral-synthesis techniques produce architectures that are power-inefficient in the interconnect. Experiments have demonstrated that in synthesized designs, about 10 to 40% of the total power may be dissipated in buses, multiplexors, and drivers. We present a novel approach targeted at the reduction of power dissipation in interconnect elements-buses, multiplexors, and buffers. The scheduling, assignment, and allocation techniques presented in this paper exploit the regularity… CONTINUE READING
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Force-directed scheduling for the behavioral synthesis of ASICs

IEEE Trans. on CAD of Integrated Circuits and Systems • 1989
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