Exploiting narrow-width values for process variationtolerant 3-D microprocessors


Process variation is a challenging problem in 3D microprocessors, since it adversely affects performance, power, and reliability of 3D microprocessors, which in turn results in yield losses. In this paper, we propose a novel architectural scheme that exploits the narrow-width value for yield improvement of last-level caches in 3D microprocessors. In a energy-/performance-efficient manner, our proposed scheme improves cache yield by 58.7% and 17.3% compared to the baseline and the naïve way-reduction scheme (that simply discards faulty cache lines), respectively.

DOI: 10.1145/2228360.2228581

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@article{Kong2012ExploitingNV, title={Exploiting narrow-width values for process variationtolerant 3-D microprocessors}, author={Joonho Kong and Sung Woo Chung}, journal={DAC Design Automation Conference 2012}, year={2012}, pages={1193-1202} }