Exploiting expendable process-margins in DRAMs for run-time performance optimization

@article{Chandrasekar2014ExploitingEP,
  title={Exploiting expendable process-margins in DRAMs for run-time performance optimization},
  author={Karthik Chandrasekar and Sven Goossens and Christian Weis and Martijn Koedam and Benny Akesson and Norbert Wehn and Kees G. W. Goossens},
  journal={2014 Design, Automation & Test in Europe Conference & Exhibition (DATE)},
  year={2014},
  pages={1-6}
}
Manufacturing-time process (P) variations and runtime voltage (V) and temperature (T) variations can affect a DRAM's performance severely. To counter these effects, DRAM vendors provide substantial design-time PVT timing margins to guarantee correct DRAM functionality under worst-case operating conditions. Unfortunately, with technology scaling these timing margins have become large and very pessimistic for a majority of the manufactured DRAMs. While run-time variations are specific to… CONTINUE READING
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An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms

  • J.Liu
  • In Proc. ISCA
  • 2013
1 Excerpt

DRAM reliability characterization by using dynamic operation stress in wafer burn-in mode

  • Il-Gweon Kim
  • In Proc. IRPS
  • 2003
1 Excerpt

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