Exploiting Speculative Thread-Level Parallelism Based on Transactional Memory


Thread level speculation (TLS) and Transactional memory (TM) are both promising way to enhance the performance of chip multiprocessor (CMP). The complexity of providing efficient memory accesses buffering mechanism in TLS can be supported by TM logically. This paper proposes a speculative multi-threading model based on transactional memory, including its… (More)
DOI: 10.1109/CMC.2011.43


7 Figures and Tables