Exploiting Parity Computation Latency for On-Chip Crosstalk Reduction

@article{Fu2010ExploitingPC,
  title={Exploiting Parity Computation Latency for On-Chip Crosstalk Reduction},
  author={Bo Fu and Paul Ampadu},
  journal={IEEE Transactions on Circuits and Systems II: Express Briefs},
  year={2010},
  volume={57},
  pages={399-403}
}
This brief provides an efficient method to address both logic errors and crosstalk-induced delay variations. In particular, the inherent skew resulting from parity generation is exploited to ensure that no two adjacent wires switch in opposite directions simultaneously, thereby reducing worst-case on-chip capacitive coupling. Data and parity-check bits are mapped to link driver registers, which are triggered by alternating clock phases. The proposed method reduces worst-case link delay by 25… CONTINUE READING

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