Executing compressed programs on an embedded RISC architecture

  title={Executing compressed programs on an embedded RISC architecture},
  author={Andrew Wolfe and Alex Chanin},
The difference in code size between RISC and CISC processors appears to be a significant factor limiting the use of RISC architectures in embedded systems. Fortunately, RISC programs can be effectively compressed. An ideal solution is to design a RISC system that can directly execute compressed programs. A new RISC system architecture called a Compressed Code RISC Processor is presented. This processor depends on a code-expanding instruction cache to manage compressed programs. The compression… CONTINUE READING
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