Excellerator: custom CMOS leaf cell layout generator

@article{Poirier1989ExcelleratorCC,
  title={Excellerator: custom CMOS leaf cell layout generator},
  author={Charles J. Poirier},
  journal={IEEE Trans. on CAD of Integrated Circuits and Systems},
  year={1989},
  volume={8},
  pages={744-755}
}
We describe a program, Excellerator, which automatically generates full custom symbolic CMOS cell layouts. The input is a transistor level netlist with optional constraints on layout shape and IIO port positions. The output is a high quality virtual-grid-based layout suitable for use in a two-dimensional tiling methodology. IIO port locations can be optimized. Versatile support for different layout shapes and port locations makes this system ideal for use in a top-down, fully automatic physical… CONTINUE READING
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