This ASIC consists of 18 channels low noise charge preamplifiers, bi-gain CRRC2 180 ns shapers, 12bit track and hold and 5 MHz output multiplexer. It covers a dynamic range of 14 bits with a linearity at the per-mil level. The preamplifier gain can be adjusted from 0.3 V/pC to 5 V/pC to accommodate various detectors. A power pulsing feature has been added in order to exploit the 1% duty cycle of the accelerator. This feature is a key parameter to embed the front-end inside the detector, without cooling pipes. It also includes a commercial 12bit ADC (AMS IP) in order to send only digital data out.