Event-driven gate-level simulation with GP-GPUs

  title={Event-driven gate-level simulation with GP-GPUs},
  author={Debapriya Chatterjee and Andrew DeOrio and Valeria Bertacco},
  journal={2009 46th ACM/IEEE Design Automation Conference},
Logic simulation is a critical component of the design tool flow in modern hardware development efforts. It is used widely -- from high-level descriptions down to gate-level ones -- to validate several aspects of the design, particularly functional correctness. Despite development houses investing vast resources in the simulation task, particularly at the gate-level, it is still far from achieving the performance demands required to validate complex modern designs. In this work, we propose the… CONTINUE READING
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Logic simulation using graphics processors

  • A. Perinkulam, S. Kundu
  • In Proc. ITSW,
  • 2007
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