Evaluation of voltage interpolation to address process variations

@article{Brownell2008EvaluationOV,
  title={Evaluation of voltage interpolation to address process variations},
  author={Kevin Brownell and Gu-Yeon Wei and David M. Brooks},
  journal={2008 IEEE/ACM International Conference on Computer-Aided Design},
  year={2008},
  pages={529-536}
}
Post-fabrication tuning provides a promising design approach to mitigate the performance and power overheads of process variation in advanced fabrication technologies. This paper explores design considerations and VLSI-CAD support for a recently proposed postfabrication tuning knob called voltage interpolation. The paper discusses design tradeoffs between circuit tuning range and static power overheads that can be performed within the synthesis flow of the design process. The paper explores the… CONTINUE READING

Citations

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Place and route considerations for voltage interpolated designs

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Automating Design of Voltage Interpolation to Address Process Variations

  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Research Narrative

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Joint Design-Time and Post-Silicon Minimization of Parametric Yield Loss using Adjustable Robust Optimization

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