Evaluation of the system-level SER performance of gigabit ethernet transceiver devices

@article{Narasimham2018EvaluationOT,
  title={Evaluation of the system-level SER performance of gigabit ethernet transceiver devices},
  author={Balaji Narasimham and Tim Wu and Jung K. Wang and Bruce Conway},
  journal={2018 IEEE International Reliability Physics Symposium (IRPS)},
  year={2018},
  pages={4C.5-1-4C.5-4}
}
System-level SER measurements were conducted on two Gigabit Ethernet transceiver devices designed in 28-nm CMOS process to evaluate the true impact of soft error upsets. Measurement results are compared with the system SER estimates based on test chip data for memory and flip-flop SER. Results indicate that most SEUs cause packet errors which are recoverable while the SER for more severe link-drop type events is significantly lower than estimates. 
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