Evaluation of a 32-bit microprocessor with built-in concurrent error-detection

  • Jiri Gaisler
  • Published 1997 in
    Proceedings of IEEE 27th International Symposium…

Abstract

This paper describes the test results from heavy ion testing of ERC32, a 32-bit processing core with on-chip concurrent error-detection. The parity based error-detection mechanisms succeeded in detecting more than 97.5% of all injected errors, significantly reducing the MTBF for undetected SEU errors. Most errors occurred in registers, but some errors in combinational logic could also be observed. The cross-section for errors in combinational logic is however too small to have an influence on the overall error rate. The conclusion is therefore that parity based error-detection is well suited to detect SEU errors in VLSI devices for space applications.

DOI: 10.1109/FTCS.1997.614076

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Cite this paper

@article{Gaisler1997EvaluationOA, title={Evaluation of a 32-bit microprocessor with built-in concurrent error-detection}, author={Jiri Gaisler}, journal={Proceedings of IEEE 27th International Symposium on Fault Tolerant Computing}, year={1997}, pages={42-46} }