Using Register Lifetime Predictions to Protect Register Files against Soft Errors
This paper describes the test results from heavy ion testing of ERC32, a 32-bit processing core with on-chip concurrent error-detection. The parity based error-detection mechanisms succeeded in detecting more than 97.5% of all injected errors, significantly reducing the MTBF for undetected SEU errors. Most errors occurred in registers, but some errors in combinational logic could also be observed. The cross-section for errors in combinational logic is however too small to have an influence on the overall error rate. The conclusion is therefore that parity based error-detection is well suited to detect SEU errors in VLSI devices for space applications.