Corpus ID: 16322370

Evaluation of Hardware Performance for the SHA-3 Candidates Using SASEBO-GII

  title={Evaluation of Hardware Performance for the SHA-3 Candidates Using SASEBO-GII},
  author={K. Kobayashi and Jun Ikegami and Shin'ichiro Matsuo and K. Sakiyama and K. Ohta},
  journal={IACR Cryptol. ePrint Arch.},
  • K. Kobayashi, Jun Ikegami, +2 authors K. Ohta
  • Published 2010
  • Computer Science
  • IACR Cryptol. ePrint Arch.
  • As a result of extensive analyses on cryptographic hash functions, NIST started an open competition for selecting a new standard hash function SHA-3. One important aspect of this competition is in evaluating hardware implementations and in collecting much attention of researchers in this area. For a fair comparison of the hardware performance, we propose an evaluation platform, a hardware design strategy, and evaluation criteria that must be consistent for all SHA-3 candidates. First, we define… CONTINUE READING
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    Publications referenced by this paper.
    A Hardware Interface for Hashing Algorithms
    • 19
    • Open Access
    Cryptographic Hash Algorithm Competition
      On Optimized FPGA Implementations of the SHA-3 Candidate Grøstl Cryptology ePrint Archive Research Center for Information Security (RCIS) " Side-channel Attack Standard Evaluation Board (SASEBO)
      • 2009
      SHA-3 Hardware Implementations