Evaluation of Architectural Alternatives to Reduce Power Consumption in a Network-on-Chip

Abstract

This work aimed at improving energy efficiency of a Network-on-Chip by applying and evaluating techniques to reduce the dynamic power dissipated by the network. Clock gating and data encoding techniques were applied in experiments based on SystemC simulation and synthesis in FPGA. Results confirmed the effectiveness of these techniques in reducing the switching activity, and identified limitations of the FPGA technology for the implementation of the evaluated techniques. Keywords-Power consumption; Network-on-Chip; FPGA.

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Cite this paper

@inproceedings{Bruch2012EvaluationOA, title={Evaluation of Architectural Alternatives to Reduce Power Consumption in a Network-on-Chip}, author={Jaison Valmor Bruch and Cesar Albenes Zeferino}, year={2012} }