Evaluation Procedures for Wafer Bonding and Thinning of Interconnect Test Structures for 3 D ICs

@inproceedings{Lu2011EvaluationPF,
  title={Evaluation Procedures for Wafer Bonding and Thinning of Interconnect Test Structures for 3 D ICs},
  author={J. J. Q. Lu and Anurag Jindal and Youngchul Kwon and John J McMahon and Marva Rasco and Rod Augur and Timothy S. Cale and Ronald J. Gutmann},
  year={2011}
}
Electrical and mechanical impacts of wafer bonding and thinning processes required for threedimensional (3D) IC fabrication have been evaluated with interconnect structures. In addition to the bonding and thinning required for a two-level 3D IC stack, an additional bonding and thinning process is used along with dielectric glue ashing to expose the previously tested interconnect structures. This procedure permits evaluation of bonding and thinning integrity without inter-wafer interconnect… CONTINUE READING
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