Evaluating the robustness of secure triple track logic through prototyping

@inproceedings{Soares2008EvaluatingTR,
  title={Evaluating the robustness of secure triple track logic through prototyping},
  author={Rafael Soares and Ney Laert Vilar Calazans and Victor Lomn{\'e} and Philippe Maurine and Lionel Torres and Michel Robert},
  booktitle={SBCCI},
  year={2008}
}
Side channel attacks are known to be efficient techniques to retrieve secret data. Within this context, this paper proposes to prototype a logic called Secure Triple Track Logic (STTL) on FPGA and evaluate its robustness against power analyses. More precisely, the paper aims at demonstrating that the basic concepts on which this logic leans are valid and… CONTINUE READING