Estimationof On-ChipSimultaneousSwitchingNoisein VDSM CMOSCircuits

  title={Estimationof On-ChipSimultaneousSwitchingNoisein VDSM CMOSCircuits},
  author={T. TangandEbyG},
  • T. TangandEbyG
  • Published 2000
On-chip simultaneous switching noise (SSN) has become an important issuein the design of power distribution networks in current VLSI/ULSI circuits. An analytical expression characterizing the simultaneousswitchingnoisevoltageis presented here basedon a lumped model. The waveform describing the SSNvoltage is quite closeto the waveform obtained fr om SPICE. The peak value of the simultaneousswitching noisevoltage based on this analytical expressionis within 10% ascompared to SPICE simulations.