Estimation of Clock Skew Using VHDL

  title={Estimation of Clock Skew Using VHDL},
  author={Vaishali Gupta and Suvarna. na and Neeraj Jain and Sarita Zutshi Bhan},
The clock signal has always been a matter of concern for most of the high–speed functions of the synchronous integrated circuits as it decides the speed regularities. To reduce the irregularities of this signal, the clock skew is one of the major constraints to be taken care of. In this paper, an efficient technique for the estimation of this clock skew has been introduced and VHDL has been used to verify its functionality. The clock skew estimation has been used to pave a way for reducing the… CONTINUE READING

Figures and Tables from this paper.


Publications referenced by this paper.

Clock Skew Reduction Using Link Region Technique,

R. Saeidi, N. Masoumi
  • 2007

Similar Papers