Estimating Architectural Resources and Performance for High-Level Synthesis Applications

Abstract

In this paper we present a solution to the following problems related to architectural synthesis. Given an input specification and a perfomance constraint, determine a lower bound number of resources (active and interconnect) required to execute the data flow graph while satisfying the performance constraint. Conversely, determine a lower bound performance… (More)
DOI: 10.1145/157485.164929

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