Escaping the Academic Sandbox: Realizing VPR Circuits on Xilinx Devices

@article{Hung2013EscapingTA,
  title={Escaping the Academic Sandbox: Realizing VPR Circuits on Xilinx Devices},
  author={Eddie Hung and Fatemeh Eslami and Steven J. E. Wilton},
  journal={2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines},
  year={2013},
  pages={45-52}
}
This paper presents a new, open-source method for FPGA CAD researchers to realize their techniques on real Xilinx devices. Specifically, we extend the Verilog-To-Routing (VTR) suite, which includes the VPR place-and-route CAD tool on which many FPGA innovations have been based, to generate working Xilinx bitstreams via the Xilinx Design Language (XDL). Currently, we can faithfully translate VPR's heterogeneous packing and placement results into an exact Xilinx `map' netlist, which is then… CONTINUE READING
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