Error Recovery in Parallel Systems of Pipelined Processors with Caches


This paper examines the problem of recovering from processor transient faults in pipelined multiprocessor systems. A pipelined machine allows out of order instruction execution and branch prediction to increase performance, thus a precise computation state may not be available. We propose a modified scheme to implement the precise computation state in a… (More)
DOI: 10.1109/ICPP.1994.105


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