Error Detection in Signed Digit Arithmetic Circuit with Parity Checker

  title={Error Detection in Signed Digit Arithmetic Circuit with Parity Checker},
  author={Gian-Carlo Cardarilli and Marco Ottavi and Salvatore Pontarelli and Marco Re and Adelio Salsano},
This paper proposes a methodology for the development of simple arithmetic self­ checking circuits using Signed Digit representation. In particular, the architecture of an adder is reported and its selfchecking capability with respect to the stuck-at fault set is shown. The main idea underlying the paper is to exploit the properties of Signed Digit representation allowing carry-free operations. In a carry free adder the parity can be easily checked allowing therefore detecting the occurrence of… CONTINUE READING


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