Erratic Bit Errors in Latches

  title={Erratic Bit Errors in Latches},
  author={P. Relangi and Subhasish Mitra},
  journal={2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual},
Erratic bit errors are caused by erratic shifts in Vmin, the minimum supply voltage at which a design can correctly operate, due to trapping/detrapping of electrons and holes in the gate oxide. The authors study the effects of erratic bit errors in latches through SPICE simulation using the gate-to-source resistive short model. The authors demonstrate that a latch structure using a redundant latch and a C-element corrects most latch erratic bit errors and significantly reduces their impact… CONTINUE READING