Equivalence Checking of SystemC and RTL Designs

Abstract

High-level languages such as C and C++ have been the standard in embedded system development. Despite having many advantages, these languages lack construct for describing hardware concepts. Hardware Description Languages (HDL), such as Verilog and VHDL, provide such low-level description, yet complexity and high design cycles hamper faster and efficient development [1, 3]. SystemC addresses both of these issues by allowing designers to develop HDL-like codes in a high-level environment by having a set of hardware-descriptive libraries [1, 2, 5]. However, RTL-based technologies such as Field-Programmable Gate Arrays (FPGA) still require HDL codes for final implementation using netlists [1]. There are SystemC-to-Verilog translation tools available, but the accuracy and functional equivalence of these tools are not well-known. Thus, the project investigates the reliability of today’s commercial and non-commercial translation tools.

10 Figures and Tables

Cite this paper

@inproceedings{Chung2009EquivalenceCO, title={Equivalence Checking of SystemC and RTL Designs}, author={Jong Yoo Chung and ByungKi Kim}, year={2009} }