Ensuring Cache Reliability and Energy Scaling at Near-Threshold Voltage With Macho

Abstract

Nanoscale process variations in conventional SRAM cells are known to limit voltage scaling in microprocessor caches. Recently, a number of novel cache architectures have been proposed which substitute faulty words of one cache line with healthy words of others, to tolerate these failures at low voltages. These schemes rely on the fault maps to identify… (More)
DOI: 10.1109/TC.2014.2339813

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