IEEE Symposium on VLSI Technology IEEE Symposium on VLSI Technology
- IEEE Symposium on VLSI Technology IEEE Symposium…
Strain engineering has become a workhorse in increasing charge carrier mobility to boost performance for sub-45nm CMOS logic technologies. While pFET transistors with embedded Si<inf>1−x</inf>Ge<inf>x</inf> layers in the S/D region have been widely employed to induce compressive strain in the silicon channel, nFET transistors have mostly depended on either tensile liners or stress memorization techniques (SMT) to introduce tensile strain. Recently, there have been reports on the use of Si:C in the nFET S/D enhancing transistor performance. In this paper we discuss results from novel ion implantation schemes employed to maximize carbon incorporation and to achieve defect free, strained Si:C layers. In addition, high activation of the dopant is maintained even in the presence of relatively high carbon incorporation. Several anneal techniques including SPE anneal, spike RTP, and laser spike anneals have been used to optimize carbon incorporation, strain and activation. Results from these different anneal techniques will be compared and discussed.