Enhancement of resolution in supply current based testing for large ICs

@article{Malaiya1991EnhancementOR,
  title={Enhancement of resolution in supply current based testing for large ICs},
  author={Yashwant K. Malaiya and Anura P. Jayasumana and Carol Q. Tong and Sankaran M. Menon},
  journal={Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's},
  year={1991},
  pages={291-296}
}
Current drawn by a static CMOS VLSI integrated circuit during quiescent periods is extremely small and is normally of the order of nanoamperes. However, it is remarkably susceptible to a number of failure modes. Many faults present in such ICs cause the quiescent power-supply current (IDDQ) to increase by several orders of magnitude. Some of these faults may not manifest as logical faults, and would not be detected by traditional IC test techniques. In large ICs, it may be hard to distinguish… CONTINUE READING

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