Enhanced wafer matching heuristics for 3-D ICs

  title={Enhanced wafer matching heuristics for 3-D ICs},
  author={Vasilis F. Pavlidis and Hu Xu and Giovanni De Micheli},
  journal={2012 17th IEEE European Test Symposium (ETS)},
Summary form only given. Pre-bond test has been identified as a vital step for the wafer level integration of 3-D ICs. The data obtained during this step can guide the subsequent manufacturing stages to improve the functional or parametric yield of the 3-D stack. The existing methods, however, do not relate directly the performance of the resulting circuits… CONTINUE READING