Enhanced testing of clock faults

@article{McLaurin2007EnhancedTO,
  title={Enhanced testing of clock faults},
  author={Teresa L. McLaurin and Rich Slobodnik and Kun-Han Tsai and Ana Keim},
  journal={2007 IEEE International Test Conference},
  year={2007},
  pages={1-9}
}
A test methodology for the control signals including clock logic, ripple reset and register file read/write control of the Cortex-A8trade high performance microprocessor core is presented. The target fault models include the stuck-at fault, transition fault and hold time fault models.