Optimal input load disturbance rejection controller design for typical integrating processes based on IMC structure
The present study suggests a disturbance estimator design method for application to a recently published, two-degree-of-freedom, control scheme for open-loop, unstable processes with time delay. A simple PID controller cascaded with a lead-lag filter replaces the high-order disturbance estimator for enhanced performance. A new analytical method on the basis of the IMC design principle, featuring only one user-defined tuning parameter, is developed for the design of the disturbance estimator. Several illustrative examples taken from previous works are included to demonstrate the superiority of the proposed disturbance estimator. The results confirm the superior performance of the proposed disturbance estimator in both nominal and robust cases. The proposed method also offers several important advantages for industrial process engineers: it covers several classes of unstable process with time delay in a unified manner, and is simple and easy to design and tune.