1 Hysteresis eects All the I SD-V G plots of our devices were accompanied by hysteresis. Fig. S1 (a) shows the channel current of Sample C as a function of gate voltage V G for V SD = 5 V. An increase in V G to 40 V is accompanied by monotonic increase in I SD from ∼1 nA to ∼100 µA. However, with decreasing V G from 40 V to zero (sequence 6-7-8), the current exhibited a hysteresis. The remnant current at V G = 0 gradually decreased, and returned to the initial value in about twelve hours. It might appear that the hysteresis is associated with trapped charges at the interface between Parylene-C and Ta 2 O 5 a behaviour resembling charge storage of oating-gate transistors, e.g., FLASH memory. However, the observed hystereses in our samples are volatile.