Energy minimization in the STT-RAM-based high-capacity last-level caches

@article{Khajekarimi2019EnergyMI,
  title={Energy minimization in the STT-RAM-based high-capacity last-level caches},
  author={Elyas Khajekarimi and Kamal Jamshidi and Abbas Vafaei},
  journal={The Journal of Supercomputing},
  year={2019},
  pages={1-24}
}
Spin-transfer torque random access memory (STT-RAM) is a suitable alternative to DRAM in the large last-level caches (L3Cs) on account of low leakage, the absence of refresh energy and good scalability. However, long latency and high energy consumption for write operations are disadvantages of this technology. The proper utilization of row buffer locality can improve energy efficiency and mitigate negative effects of writing operations in the STT-RAM L3Cs. In this paper, we present an integer… CONTINUE READING

Figures, Tables, Results, and Topics from this paper.

Key Quantitative Results

  • Evaluations demonstrate that on average, our ILP model reduces dynamic energy about 19% and improves row buffer hit rate about 23% compared to the state of the art.
  • The experimental results show that on average, compared to the state of the art, our ILP model saves dynamic energy about 19%, decreases the number of write operations in the STT-RAM data array about 25%, increases RB-hit rate about 23% and reduces about 47% of the number of RB-conflicts.
  • The evaluations demonstrate that on average, the proposed heuristic algorithm decreases the dynamic energy consumption more than 12% and reduces the number of write operations in the STT-RAM data array about 16% compared to the state of the art.
  • 8, on average the RESA technique has more than 44% energy improvement compared to the traditional technique and also more than 12% improvement in energy compared to the AAB technique.
  • On average, the MECIL technique improves RB-hit rate about 49% and 23% compared to traditional and AAB techniques, respectively.

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