Energy-efficient partitioning of hybrid caches in multi-core architecture

@inproceedings{Lee2014EnergyefficientPO,
  title={Energy-efficient partitioning of hybrid caches in multi-core architecture},
  author={Dongwook Lee and Kiyoung Choi},
  booktitle={VLSI-SoC},
  year={2014}
}
This chapter presents a technique for reducing energy consumed by hybrid caches that have both SRAM and STT-RAM (SpinTransfer Torque RAM) in multi-core architecture. It is based on dynamic way partitioning of the SRAM cache as well as the STT-RAM cache. Each core is allocated with a specific number of ways consisting of SRAM ways and STT-RAM ways. Then a cache miss fills the corresponding block in the SRAM or STT-RAM region based on an existing technique called read-write aware region-based… 

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