• DOI:10.1109/VLSI-SoC.2014.7004174
• Corpus ID: 6518681

Energy-efficient partitioning of hybrid caches in multi-core architecture

@inproceedings{Lee2014EnergyefficientPO,
  title={Energy-efficient partitioning of hybrid caches in multi-core architecture},
  author={Dongwook Lee and Kiyoung Choi},
  booktitle={VLSI-SoC},
  year={2014}
}

• Dongwook Lee, Kiyoung Choi
• Published in VLSI-SoC 2014
• Computer Science

This chapter presents a technique for reducing energy consumed by hybrid caches that have both SRAM and STT-RAM (SpinTransfer Torque RAM) in multi-core architecture. It is based on dynamic way partitioning of the SRAM cache as well as the STT-RAM cache. Each core is allocated with a specific number of ways consisting of SRAM ways and STT-RAM ways. Then a cache miss fills the corresponding block in the SRAM or STT-RAM region based on an existing technique called read-write aware region-based hybrid cache architecture. Thus, when a store operation from a core causes an L2 cache miss (store miss), the block is assigned to the SRAM cache. When a load operation from a core causes an L2 cache miss (load miss) and thus causes a block fill, the block is assigned to the STT-RAM cache. However, if all the allocated ways are already placed in the SRAM, then the block fill is done into the SRAM regardless of store or load miss. The partitioning decision is updated periodically. We further improve our technique by adopting the so called allocation switching technique to avoid too much unbalanced use of SRAM or STT-RAM. Simulation results show that the proposed technique improves the performance of the multi-core architecture and significantly reduces energy consumption in the hybrid caches compared to the state-of-the-art migration-based hybrid cache management.