Energy-efficient Spin-Transfer Torque RAM cache exploiting additional all-zero-data flags

  title={Energy-efficient Spin-Transfer Torque RAM cache exploiting additional all-zero-data flags},
  author={Jinwook Jung and Yohei Nakata and Masahiko Yoshimoto and Hiroshi Kawaguchi},
  journal={International Symposium on Quality Electronic Design (ISQED)},
Large on-chip caches account for a considerable fraction of the total energy consumption in modern microprocessors. In this context, emerging Spin-Transfer Torque RAM (STT-RAM) has been regarded as a promising candidate to replace large on-chip SRAM caches in virtue of its nature of the zero leakage. However, large energy requirement of STT-RAM on write operations, resulting in a huge amount of dynamic energy consumption, precludes it from application to on-chip cache designs. In order to… CONTINUE READING


Publications citing this paper.
Showing 1-9 of 9 extracted citations


Publications referenced by this paper.
Showing 1-10 of 23 references

The gem5 Simulator

  • N. Binkert
  • ACM SIGARCH Computer Architecture News, vol. 39…
  • 2011
1 Excerpt

Similar Papers

Loading similar papers…