Energy-efficient Spin-Transfer Torque RAM cache exploiting additional all-zero-data flags

@article{Jung2013EnergyefficientST,
  title={Energy-efficient Spin-Transfer Torque RAM cache exploiting additional all-zero-data flags},
  author={Jinwook Jung and Yohei Nakata and Masahiko Yoshimoto and Hiroshi Kawaguchi},
  journal={International Symposium on Quality Electronic Design (ISQED)},
  year={2013},
  pages={216-222}
}
Large on-chip caches account for a considerable fraction of the total energy consumption in modern microprocessors. In this context, emerging Spin-Transfer Torque RAM (STT-RAM) has been regarded as a promising candidate to replace large on-chip SRAM caches in virtue of its nature of the zero leakage. However, large energy requirement of STT-RAM on write operations, resulting in a huge amount of dynamic energy consumption, precludes it from application to on-chip cache designs. In order to… CONTINUE READING

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