Energy and area saving effect of Dynamic Partial Reconfiguration on a 28-nm process FPGA

Abstract

We empirically evaluated the energy- and area-saving effect of Dynamic Partial Reconfiguration (DPR) of a 28-nm process FPGA. DPR is a technology where a portion of the entire circuit is replaced with another one, while the other parts of the circuit still continue running. Using DPR, different functionalities are not necessarily implemented at once; only… (More)
DOI: 10.1109/GCCE.2013.6664803

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