Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems

@inproceedings{Ferri2010EnergyAT,
  title={Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems},
  author={C. Ferri and S. Wood and Tali Moreshet and R. I. Bahar and M. Herlihy},
  booktitle={HiPEAC},
  year={2010}
}
  • C. Ferri, S. Wood, +2 authors M. Herlihy
  • Published in HiPEAC 2010
  • Computer Science
  • We propose a new design for an energy-efficient hardware transactional memory (HTM) system for power-aware embedded devices. Prior hardware transactional memory designs proposed a small, fully-associative transactional cache at the same level as the L1 cache. We propose an alternative design that unifies the transactional and L1 caches, and provides a small victim cache to reduce effects of capacity and conflict evictions. We evaluate our new HTM scheme on a variety of benchmarks, both in terms… CONTINUE READING
    13 Citations
    Evaluation of a hardware transactional memory model in an NoC-based embedded MPSoC
    • 6
    Lock Elision for Memcached: Power and Performance analysis on an Embedded Platform
    • 2
    • PDF
    Improving the efficiency of a hardware transactional memory on an NoC-based MPSoC
    • 3
    • PDF
    Optimizing throughput/power trade-offs in hardware transactional memory using DVFS and intelligent scheduling
    • 5
    • PDF
    Energy-Efficient and High-Performance Lock Speculation Hardware for Embedded Multicore Systems
    • 4
    • PDF
    Selective dynamic serialization for reducing energy consumption in hardware transactional memory systems
    • 4
    TxSnoop: Power-Aware Transactional Snoop
    • Ehsan Atoofian
    • Computer Science
    • 2013 12th IEEE International Conference on Trust, Security and Privacy in Computing and Communications
    • 2013
    Hierarchical Transactional Memory Protocol for Distributed Mixed-Criticality Embedded Systems
    • Zaher Owda, Moises Urbina, R. Obermaisser, M. Abuteir
    • Computer Science
    • 2016 IEEE 14th Intl Conf on Dependable, Autonomic and Secure Computing, 14th Intl Conf on Pervasive Intelligence and Computing, 2nd Intl Conf on Big Data Intelligence and Computing and Cyber Science and Technology Congress(DASC/PiCom/DataCom/CyberSciTech)
    • 2016
    • 3
    • PDF
    Adaptive Snoop Granularity and Transactional Snoop Filtering in Hardware Transactional Memory
    • Ehsan Atoofian
    • Computer Science
    • Canadian Journal of Electrical and Computer Engineering
    • 2014

    References

    SHOWING 1-10 OF 30 REFERENCES
    Energy efficient synchronization techniques for embedded architectures
    • 19
    • PDF
    Power and performance tradeoffs using various caching strategies
    • R. I. Bahar, G. Albera, S. Manne
    • Computer Science
    • Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379)
    • 1998
    • 144
    • PDF
    Cache coherence tradeoffs in shared-memory MPSoCs
    • 52
    • PDF
    Scratchpad memory: a design alternative for cache on-chip memory in embedded systems
    • 722
    • PDF
    An adaptive serial-parallel CAM architecture for low-power cache blocks
    • 54
    • PDF
    Latency and bandwidth efficient communication through system customization for embedded multiprocessors
    • C. Yu, P. Petrov
    • Computer Science
    • 2008 45th ACM/IEEE Design Automation Conference
    • 2008
    • 6
    Hybrid transactional memory
    • 463
    • PDF
    Virtualizing transactional memory
    • 346
    • PDF
    Power/Performance Hardware Optimization for Synchronization Intensive Applications in MPSoCs
    • 28
    Software transactional memory
    • 1,062