Energy-Efficient Neuron, Synapse and STDP Integrated Circuits

@article{CruzAlbrecht2012EnergyEfficientNS,
  title={Energy-Efficient Neuron, Synapse and STDP Integrated Circuits},
  author={Jose M. Cruz-Albrecht and Michael W. Yung and Narayan Srinivasa},
  journal={IEEE Transactions on Biomedical Circuits and Systems},
  year={2012},
  volume={6},
  pages={246-256}
}
Ultra-low energy biologically-inspired neuron and synapse integrated circuits are presented. The synapse includes a spike timing dependent plasticity (STDP) learning rule circuit. These circuits have been designed, fabricated and tested using a 90 nm CMOS process. Experimental measurements demonstrate proper operation. The neuron and the synapse with STDP circuits have an energy consumption of around 0.4 pJ per spike and synaptic operation respectively. 
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