End-to-end scalable FPGA accelerator for deep residual networks

@article{Ma2017EndtoendSF,
  title={End-to-end scalable FPGA accelerator for deep residual networks},
  author={Yufei Ma and Minkyu Kim and Yu Cao and Sarma B. K. Vrudhula and Jae-sun Seo},
  journal={2017 IEEE International Symposium on Circuits and Systems (ISCAS)},
  year={2017},
  pages={1-4}
}
This work presents an efficient hardware accelerator design of deep residual learning algorithms, which have shown superior image recognition accuracy (>90% top-5 accuracy on ImageNet database). Two key objectives of the acceleration strategy are to (1) maximize resource utilization and minimize data movements, and (2) employ scalable and reusable computing primitives to optimize physical design under hardware constraints. Furthermore, we present techniques for efficient integration and… CONTINUE READING
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