Enabling sizing for enhancing the static noise margins


This paper suggests a transistor sizing method for classical CMOS gates implemented in advanced technology nodes and operating at low voltages. The method relies on upsizing the length (L) of all transistors uniformly, and balancing the voltage transfer curves (VTCs) for maximizing the static noise margins (SNMs). We use the most well-known CMOS gates (INV… (More)
DOI: 10.1109/ISQED.2013.6523623


11 Figures and Tables