Enabling SOI-based assembly technology for three-dimensional (3d) integrated circuits (ICs)

@article{Topol2005EnablingSA,
  title={Enabling SOI-based assembly technology for three-dimensional (3d) integrated circuits (ICs)},
  author={A. Topol and D. C. La Tulipe and Lcathen Shi and S. M. Alam and D. J. Frank and S. E. Steen and James Vichiconti and Dominick Posillico and Michael D. Cobb and S. Medd and Jaydeep A. Patel and Sergio Goma and D. Dimilia and M. Robson and E. Duch and Matthew Farinelli and Caiyuan Wang and R. Conti and D. M. Canaperi and Lili Deligianni and Abhishek Kumar and K. T. Kwietniak and C. D'emic and J. A. Ott and A. M. Young and K. Guarini and Meikei Ieong},
  journal={IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.},
  year={2005},
  pages={352-355}
}
We present solutions to the key process technology challenges of three-dimensional (3D) integrated circuits (ICs) that enable creation of stacked device layers with the shortest distance between them, the highest interconnection density and extremely aggressive wafer-to-wafer alignment. To achieve this important 3D IC technology milestone, we optimized the layer transfer process to include a glass handle wafer, oxide fusion bonding, wafer bow compensation methods, and a single damascene… CONTINUE READING
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