Enabling 3D-IC foundry technologies for 28 nm node and beyond: through-silicon-via integration with high throughput die-to-wafer stacking

@article{Chen2009Enabling3F,
  title={Enabling 3D-IC foundry technologies for 28 nm node and beyond: through-silicon-via integration with high throughput die-to-wafer stacking},
  author={D.Y. Chen and W. C. Chiou and M.F. Chen and T. Wang and K. M. Ching and H.J. Tu and W.J. Wu and C.-L. Yu and K.F. Yang and H.B. Chang and Ming-Huei Tseng and C.W. Hsiao and Y.J. Lu and H.P. Hu and Y.C. Lin and C.-S. Hsu and W.S. Shue and C.H. Yu},
  journal={2009 IEEE International Electron Devices Meeting (IEDM)},
  year={2009},
  pages={1-4}
}
  • D.Y. Chen, W. Chiou, +15 authors C. Yu
  • Published 1 December 2009
  • Materials Science
  • 2009 IEEE International Electron Devices Meeting (IEDM)
High density through-silicon-via (TSV) and cost-effective 3D die-to-wafer integration scheme are proposed as best-in-class foundry solutions for high-end CMOS chips at 28 nm node and beyond. Key processes include: TSV formation, extreme thinning of the TSV wafer and die-to-wafer assembly. The impact of extreme thinning on device threshold voltage, leakage currents, and Ion-Ioff characteristics of bulk CMOS devices with and without e-SiGe/CESL stressors has been minimized. The presence of TSV… Expand
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References

Three-dimensional wafer stacking via Cu-Cu bonding integrated with 65-nm strained-Si/low-k CMOS technology
The authors report the first demonstration of integrating wafer stacking via Cu bonding with strained-Si/low-k 65-nm CMOS technology. Sets of 330 mm wafers with active devices such as 65-nm MOSFETsExpand