Embedded memory reliability: the SER challenge

  title={Embedded memory reliability: the SER challenge},
  author={N. Derhacobian and Valery A. Vardanian and Yervant Zorian},
  journal={Records of the 2004 International Workshop on Memory Technology, Design and Testing, 2004.},
Drastic decreases in device dimensions and power supply have significantly reduced noise margins and challenged the reliability of very deep-submicron chips. Soft error rate is the main cause behind this challenge. Even though both logic block and embedded memories are impacted by this challenge, but the failure rate in embedded memories remains dominant and requires infrastructure IP for self-correctness. ECC is such an IP. It operates in the field during normal mode operation of a chip. The… CONTINUE READING
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