Electronic architecture for an analog retinal processing prototype suitable to be implemented on standard CMOS technology

Abstract

An analog architecture of optic signal processing is presented in this work, with the goal to emulate one of the much processes involved in a biological retina. Here we have considered that the receptive field is the main unit of processing in the visual system. So, the proposed architecture tries to give partial solution to the properties of a receptive field in order to give some help to people with retinal diseases in the future. A receptive field is represented by an array of 3×3 pixels and four main mathematical operations are carried out on each one pixel. This means that image processing is developed at pixel level. Operations involved are: (1) photo-transduction by photocurrent integration; (2) Average of the signals coming from the eight neighbouring pixels, obtained by a neu-NMOS (v-NMOS) neuron; (3) The gradient between central pixel and the average value from neighboring pixels. This operation is done by a comparator; (4) a generator of impulses whose density is proportional to the gradient. The coupling methodology among every block or module, and the PSPICE simulation using the technology parameters of 0.5µm are the main objectives in this work.

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Cite this paper

@article{CastilloCabrera2011ElectronicAF, title={Electronic architecture for an analog retinal processing prototype suitable to be implemented on standard CMOS technology}, author={G. Castillo-Cabrera and M. A. Reyes-Barranca and J. Garcia-Lamont and J. Antonio Moreno-Cadenas and L. Martin Flores-Nava}, journal={2011 8th International Conference on Electrical Engineering, Computing Science and Automatic Control}, year={2011}, pages={1-6} }