Electronic alignment for proximity communication

  title={Electronic alignment for proximity communication},
  author={R. T. Drost and Ron Ho and Dean A. Hopkins and I. Sutherland},
  journal={2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)},
  pages={144-518 Vol.1}
This work presents an electronic alignment mechanism for capacitively-coupled proximity communication. On an experimental chip, position offsets of up to +/-100/spl mu/m are electrically corrected to within 6.25/spl mu/m. A 0.35/spl mu/m experimental CMOS chip communicates at 1.35Gb/s with a BER /spl les/10/sup -10/. 
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