Electromigration modeling and full-chip reliability analysis for BEOL interconnect in TSV-based 3D ICs

@article{Pathak2011ElectromigrationMA,
  title={Electromigration modeling and full-chip reliability analysis for BEOL interconnect in TSV-based 3D ICs},
  author={Mohit Pathak and Jiwoo Pak and David Z. Pan and Sung Kyu Lim},
  journal={2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)},
  year={2011},
  pages={555-562}
}
Electromigration (EM) is a critical problem for interconnect reliability of modern integrated circuits (ICs), especially as the feature size becomes smaller. In three-dimensional (3D) IC technology, the EM problem becomes more severe due to drastic dimension mismatches between metal wires, through silicon vias (TSVs), and landing pads. Meanwhile, the thermo-mechanical stress due to the TSV can also cause reduction in the failure time of wires. However, there is very little study on EM issues… CONTINUE READING
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