Electrically erasable and reprogrammable read-only memory using the n-channel SIMOS one-transistor cell

  title={Electrically erasable and reprogrammable read-only memory using the n-channel SIMOS one-transistor cell},
  author={B. Rossler},
  journal={IEEE Transactions on Electron Devices},
  • B. Rossler
  • Published 1 May 1977
  • Engineering
  • IEEE Transactions on Electron Devices
The stacked-gate injection MOS transistor (SIMOS) uses a control gate stacked on the floating gate for selection of the cell during reading, programming, and erasure. Programming is achieved by the injection of hot electrons from the channel into the floating gate, resulting in a large upward shift in threshold voltage. In both states, operation is in the enhancement mode. Electrical erasure can be performed by injection of hot holes from an avalanche breakdown at the source-substrate junction… 

Figures from this paper

An 8192-bit electrically alterable ROM employing a one-transistor cell with floating gate
Describes a fully decoded, TTL compatible, electrically alterable, 8-kbit MOS ROM using a two-level n-channel polysilicon gate process that operates with standard voltages during read, program and erase operation, and a single pulsed high voltage for programming.
A two-transistor SIMOS EAROM cell
A new, electrically alterable, nonvolatile memory cell, consisting of a floating gate memory transistor and an access transistor, has been developed using the self-aligned n-channel stacked-gate
Technology of a new n-channel one-transistor EAROM cell called SIMOS
The structure and technology of a new nonvolatile charge-storage device are described. The stacked-gate injection MOS (SIMOS) device is an n-channel MOS transistor with a control gate stacked on the
An 8K EEPROM using the SIMOS storage cell
  • B. Giebel
  • Engineering
    IEEE Journal of Solid-State Circuits
  • 1980
An 8192 bit MOS floating-gate EEPROM has been developed and transferred to volume production and special circuit design ensures programmability of deeply erased cells and avoids electrical stress to the cell unintentionally affecting the programmed information.
Low-voltage single supply CMOS electrically erasable read-only memory
A low-voltage single supply CMOS electrically erasable read-only memory (CMOS-EEROM) is described. It combines long-term charge retention and the possibility of being read, written, and erased from a
Technology of a New n-Char'mel One-Transistor EAROM Cell
an n-channel MOS transistor with a cont~~'ud gate stacked on the floating gate. In the programming mode, elNf!ctrons are accelerated by the channel drift field to energies hiilrlh enough to overcome
Low-voltage alterable EAROM cells with nitride-barrier avalanche-injection MIS (NAMIS)
Design and characteristics of NAMIS-EAROM cells alterable with voltages of about 10 V are demonstrated. The NAMIS cell employs a very thin silicon nitride film grown by direct thermal nitridation of
Electrically Alterable MOS-ROMs, with Particular Emphasis on the Floating Gate Type
The intent of this paper is to discuss the latest developments in the nonvolatile semiconductor memories sector, namely the EAROMs, which are memory devices programmable and erasable by purely electrical means.
Chapter 1 Basics of Nonvolatile Semiconductor Memory Devices
Since the very first days of the mid-1960s, when the potential of metal-oxide semiconductor (MOS) technology to realize semiconductor memories with superior density and performance than would ever be
Electrically alterable 8192 bit N-channel MOS PROM
This paper will describe an 8192-bit N-channel EAROM featuring a single transistor cell, standard operating voltages and single high voltage pulse for programming and erasure, and low standby power.


Electrically reprogrammable nonvolatile semiconductor memory
Electrically reprogrammable nonvolatile memories using avalanche injection of electrons and holes into a floating gate are described and the results of measurement on fabricated devices are shown.
Carrier mobility and current saturation in the MOS transistor
Consideration is given to the phenomenon of saturation of drain current in the insulated-gate field-effect transistor. The effect of limited carrier drift velocity in the transistor channel is
Carrier mobility and current sal 11- 2311f
  • 1975
Proposal of electrically repro - grammable , nonvolatile semiconductor memory , ”
  • 1974