Electrically alterable avalanche-injection-type MOS READ-ONLY memory with stacked-gate structure

@article{Iizuka1976ElectricallyAA,
  title={Electrically alterable avalanche-injection-type MOS READ-ONLY memory with stacked-gate structure},
  author={Hisakazu Iizuka and Fujio Masuoka and Tai Sato and Masaoki Ishikawa},
  journal={IEEE Transactions on Electron Devices},
  year={1976},
  volume={23},
  pages={379-387}
}
Design theory and experimental results of the WRITE and ERASE properties of a rewritable and nonvolatile avalanche-injection-type memory are reported. The memory transistor has the stacked-gate structure of a floating gate and a control gate. The threshold-voltage shift of the transistor due to injected charge is controlled by applied potential on the control gate which reduces the avalanche breakdown voltage of the drain junction and accelerates electron injection into the floating gate. The… 

An Electrically Using Alterable Nonvolatile Memory Cell a Floating-Gate Structure

An electrically alterable, floating-gate, nonvolatile memory transistor has been developed, with a cell area of under 500 Urn*, and using an advanced n-channel, polysilicon gate process. Cell

DIFMOS—A floating-gate electrically erasable nonvolatile semiconductor memory technology

  • W. Gosney
  • Engineering
    IEEE Transactions on Electron Devices
  • 1977
Electrically alterable read-only memories (EAROM's) or reprogrammable read-only memories (RPROM's) can be fabricated using a single-level metal-gate p-channel MOS technology with all conventional

An electrically alterable nonvolatile memory cell using a floating-gate structure

Analysis of experimental data shows that electrical erase does change programming characteristics significantly, and must be accounted for in circuit design, and a 5-V, 16K high-speed EAROM has been developed which shows successful programming and erase behaviour at nominal voltages of 25 and 35 V.

FCAT-II: A 50 ns/15 V alterable nonvolatile memory device—Part I: Experimental

A new structure for an n-channel Floating Si-gate Channel Corner Avalanche Transition nonvolatile memory device (FCAT-II) and its novel write-erase characteristics are described, making Fowler-Nordheim tunneling the major electron injection mechanism in the floating gate.

Single Transistor lectrical

A novel single transistor electrically alterable memory cell is presented. The cell is based on floating gate technology using a double diffused (DMOS) transistor. Writing into the cell is achieved

Low-voltage alterable EAROM cells with nitride-barrier avalanche-injection MIS (NAMIS)

Design and characteristics of NAMIS-EAROM cells alterable with voltages of about 10 V are demonstrated. The NAMIS cell employs a very thin silicon nitride film grown by direct thermal nitridation of

Low-voltage single supply CMOS electrically erasable read-only memory

A low-voltage single supply CMOS electrically erasable read-only memory (CMOS-EEROM) is described. It combines long-term charge retention and the possibility of being read, written, and erased from a

FCAT—A low-voltage high-speed alterable n-channel nonvolatile memory device

The structure and principles of a new nonvolatile charge storage device are described. The Floating Si-gate Channel Corner Avalanche Transition (FCAT) memory device is an n-channel MOS transistor

Technology of a new n-channel one-transistor EAROM cell called SIMOS

The structure and technology of a new nonvolatile charge-storage device are described. The stacked-gate injection MOS (SIMOS) device is an n-channel MOS transistor with a control gate stacked on the

A high-density, high-performance EEPROM cell

The theory, design, and performance data of a new high density, high performanee EEPROM cell is described. The memory cell is fabricated using standard n-channel double-polysilicon processing
...

References

SHOWING 1-6 OF 6 REFERENCES

A New Instability in MOS Transistor Caused by Hot Electron and Hole Injection from Drain Avalanche Plasma into Gate Oxide

Results of an experimental study are reported of a new instability found in p- and n-channel MOS transistors. This phenomenon is that when a higher voltage in an excess of a brakdown voltage is

Fowler‐Nordheim Tunneling into Thermally Grown SiO2

Electronic conduction in thermally grown SiO2 has been shown to be limited by Fowler‐Nordheim emission, i.e., tunneling of electrons from the vicinity of the electrode Fermi level through the

Barrier Inhomogeneities on a Si–SiO2 Interface by Scanning Internal Photoemission

Scanning internal photoemission has been used to map barrier inhomogeneities in a sodium‐contaminated Si–SiO2 interface. The interface barrier is lowered in local regions at which sodium accumulates.