• DOI:10.1109/T-ED.1976.18415
• Corpus ID: 30491074

Electrically alterable avalanche-injection-type MOS READ-ONLY memory with stacked-gate structure

@article{Iizuka1976ElectricallyAA,
  title={Electrically alterable avalanche-injection-type MOS READ-ONLY memory with stacked-gate structure},
  author={Hisakazu Iizuka and Fujio Masuoka and Tai Sato and Masaoki Ishikawa},
  journal={IEEE Transactions on Electron Devices},
  year={1976},
  volume={23},
  pages={379-387}
}

• H. Iizuka, F. Masuoka, +1 author M. Ishikawa
• Published 1 April 1976
• Engineering
• IEEE Transactions on Electron Devices

Design theory and experimental results of the WRITE and ERASE properties of a rewritable and nonvolatile avalanche-injection-type memory are reported. The memory transistor has the stacked-gate structure of a floating gate and a control gate. The threshold-voltage shift of the transistor due to injected charge is controlled by applied potential on the control gate which reduces the avalanche breakdown voltage of the drain junction and accelerates electron injection into the floating gate. The writing time is about 20 µs for a single transistor and is less than 5 s for a fully decoded 2048-bit memory with appropriate duty cycles of programming pulses. Erasure of the memory is accomplished either by ultraviolet light irradiation onto the floating gate or by electric field emission of electrons from the floating gate to the control gate. Electrical erasing is theoretically analyzed and successfully compared with experimental results on the 2K bit memory. Memory retention is also investigated and a charge-escaping model is proposed.