Electrical and thermal scaling trends for SOI FinFET ESD design

@article{Thijs2009ElectricalAT,
  title={Electrical and thermal scaling trends for SOI FinFET ESD design},
  author={Steven Thijs and David Tr{\'e}mouilles and Alessio Griffoni and Christian Russ and Dimitri Linten and Mirko Scholz and Nadine Collaert and Rita Rooyackers and Charvaka Duvvury and Guido Groeseneken},
  journal={2009 31st EOS/ESD Symposium},
  year={2009},
  pages={1-8}
}
This paper first presents an analysis of the holding voltage of NMOS and PMOS SOI FinFETs in bipolar mode. Further, to make FinFETs an area-efficient technology option, geometrical parameters which are fixed by the current process will be scaled down. A TCAD simulation methodology is used to predict the robustness of scaled-down FinFETs.