Electrical and physical analysis of a 28nm FPGA programmable delay circuit single tap delay failure


This failure analysis is based on a 28nm FPGA IDelay logic block which features an all programmable, 32-tap delay line. Each tap delay is carefully calibrated to provide an absolute delay value of 78ps independent of process voltage, and temperature variations. To locate the failing IDelay site, scan chain methodology was utilized. Combinations of delay… (More)

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